This invention relates to a semiconductor device, particularly, a technique effective when adapted to a semiconductor device having a trench-gate structure.
A power transistor has been used for various applications including a power amplifier circuit, power supply circuit, converter and power supply protective circuit. Since it treats high power, it is required to have high breakdown voltage and to permit high current.
In the case of MISFET (Metal Insulator Semiconductor Field Effect Transistor), high current can be attained easily by an expansion of a channel width. In order to avoid an increase in a chip area caused by such expansion of a channel width, a mesh-gate structure is, for example, employed.
Gates are two-dimensionally arranged in the form of a lattice in the mesh-gate structure so that a channel width per unit chip area can be enlarged. A description of an FET having a mesh-gate structure can be found on pages 429 to 430 of xe2x80x9cSemiconductor Handbookxe2x80x9d published by Ohmsha Limited or U.S. Pat. No. 5,940,721.
For such a power FET, a planar structure has conventionally been employed because its fabrication process is simple and an oxide film which will serve as a gate insulating film can be formed easily. In the above-described U.S. Pat. No. 5,940,721, shown is an FET having a planar structure.
The FET having a planar structure is however accompanied with the drawbacks that when a gate is formed narrowly, a channel length becomes short and a short-channel effect appears because the channel length is determined depending on the gate length; or when a gate is formed narrowly, an allowable current decreases because the gate has additionally a function of interconnection. It is therefore impossible to conduct miniaturization freely. With the foregoing in view, adoption of an FET having a trench-gate structure is considered because it can improve the integration degree of cells and in addition, reduce an on resistance.
The trench-gate structure is formed by disposing, via an insulating film, a conductive layer, which will serve as a gate, in a trench extended in the main surface of a semiconductor substrate and in this structure, the deeper portion and the outer surface portion of the main surface serve as a drain region and a source region, respectively and a semiconductor layer between the drain and source regions serves as a channel forming region.
An MISFET having such a trench-gate structure is disclosed, for example, in Japanese Patent Application Laid-Open No. Hei 8-23092 or U.S. Pat. No. 5,918,114.
With an advance of the miniaturization of a device, there is a tendency to make the source region shallower. When the source region becomes shallower, however, it becomes difficult to place a trench gate at a precise position and the end portion of the trench gate does not overlap with the source region. If a source offset occurs, in other words, the trench gate gets out of the source region, by inaccurate positioning of the trench gate, this source offset impairs the functioning of the FET.
Since the end portion of the gate insulating film is positioned at the corner of the trench, it is sometimes damaged during the formation of a trench gate. Such an inferior gate insulating film happens to cause operation failure of the device.
An object of the present invention is to provide a technique capable of overcoming the above-described problems and preventing the occurrence of a source offset.
Another object of the present invention is to provide a technique capable of overcoming the above-described problems and preventing the damage of a gate insulating film.
A further object of the present invention is to provide a FET having a thinned trench-gate structure.
The above-described and the other objects and novel features of the present invention will be apparent from the description herein and accompanying drawings.
Among the inventions disclosed by the present application, representative ones will next be summarized simply.
In a semiconductor device equipped with an FET having a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, a trench-gate conductive layer (gate electrode) and a gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench.
A fabrication method of the above-described semiconductor device comprises forming an insulating film over the main surface of the semiconductor substrate, patterning the insulating film according to a pattern corresponding to the trench-gate, that is, gate electrode, forming a trench, wherein a trench-gate will be formed, in the semiconductor substrate with the patterned insulating film as a mask, etching the side surface of the insulating film by isotropic etching to cause it retreat from the upper end portion of the trench, forming a gate insulating film and a conductive layer, which will be a trench gate, in the trench and over the main surface of the semiconductor substrate at the periphery of the trench, and then forming a channel forming region and a source region to be brought into contact with the gate insulating film in the trench.
In the above-described means, the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate, which makes it possible to prevent occurrence of a source offset. In addition, a gate insulating film and a conductive film which will be a trench gate are formed over the main surface of the semiconductor substrate at the periphery of the trench so that it is possible to prevent the damage at the end portion of the gate insulating film.